
`timescale 1ns/1ps 

module simu();

reg clk;
initial begin 
  clk = 0;
  forever begin
    #(4) clk = ~clk;
  end
end

reg reset;
initial begin
  reset = 0;
  #10;
  reset = 1;
  #80;
  reset = 0;
end

wire default_250mhz_clk1_clk_n;
wire default_250mhz_clk1_clk_p;

assign default_250mhz_clk1_clk_p = clk;
assign default_250mhz_clk1_clk_n = ~clk;



wire          ddr4_sdram_c1_083_act_n;
wire [16:0]   ddr4_sdram_c1_083_adr;
wire [1:0]    ddr4_sdram_c1_083_ba;
wire          ddr4_sdram_c1_083_bg;
wire          ddr4_sdram_c1_083_ck_c;
wire          ddr4_sdram_c1_083_ck_t;
wire          ddr4_sdram_c1_083_cke;
wire          ddr4_sdram_c1_083_cs_n;
wire [7:0]    ddr4_sdram_c1_083_dm_n;
wire [63:0]   ddr4_sdram_c1_083_dq;
wire [7:0]    ddr4_sdram_c1_083_dqs_c;
wire [7:0]    ddr4_sdram_c1_083_dqs_t;
wire          ddr4_sdram_c1_083_odt;
wire          ddr4_sdram_c1_083_reset_n;

wire           rs232_uart_rxd;
wire           rs232_uart_txd;
wire           spi_flash_io0_io;
wire           spi_flash_io1_io;
wire           spi_flash_io2_io;
wire           spi_flash_io3_io;
wire           spi_flash_ss_io;


Soc_xlnx soc_xlnx(
    .ddr4_sdram_c1_083_act_n(ddr4_sdram_c1_083_act_n),
    .ddr4_sdram_c1_083_adr(ddr4_sdram_c1_083_adr),
    .ddr4_sdram_c1_083_ba(ddr4_sdram_c1_083_ba),
    .ddr4_sdram_c1_083_bg(ddr4_sdram_c1_083_bg),
    .ddr4_sdram_c1_083_ck_c(ddr4_sdram_c1_083_ck_c),
    .ddr4_sdram_c1_083_ck_t(ddr4_sdram_c1_083_ck_t),
    .ddr4_sdram_c1_083_cke(ddr4_sdram_c1_083_cke),
    .ddr4_sdram_c1_083_cs_n(ddr4_sdram_c1_083_cs_n),
    .ddr4_sdram_c1_083_dm_n(ddr4_sdram_c1_083_dm_n),
    .ddr4_sdram_c1_083_dq(ddr4_sdram_c1_083_dq),
    .ddr4_sdram_c1_083_dqs_c(ddr4_sdram_c1_083_dqs_c),
    .ddr4_sdram_c1_083_dqs_t(ddr4_sdram_c1_083_dqs_t),
    .ddr4_sdram_c1_083_odt(ddr4_sdram_c1_083_odt),
    .ddr4_sdram_c1_083_reset_n(ddr4_sdram_c1_083_reset_n),
    .default_250mhz_clk1_clk_n(default_250mhz_clk1_clk_n),
    .default_250mhz_clk1_clk_p(default_250mhz_clk1_clk_p),
    .reset(reset),
    .spi_flash_io0_io(spi_flash_io0_io),
    .spi_flash_io1_io(spi_flash_io1_io),
    .spi_flash_io2_io(spi_flash_io2_io),
    .spi_flash_io3_io(spi_flash_io3_io),
    .spi_flash_ss_io(spi_flash_ss_io),
    .rs232_uart_rxd(rs232_uart_rxd),
    .rs232_uart_txd(rs232_uart_txd)
    );


endmodule